86 lines
No EOL
2.5 KiB
Rust
86 lines
No EOL
2.5 KiB
Rust
//use crate::kernelvec::*;
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//use crate::memlayout::*;
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//use crate::param::NCPU;
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//use super::main::*;
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//use crate::riscv::registers::{pmpcfg0::*, *};
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use core::arch::asm;
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use core::hint::unreachable_unchecked;
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mod riscv;
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#[repr(C, align(16))]
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struct Stack([u8; 4096 * 4 * NCPU]);
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#[no_mangle]
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static mut STACK0: Stack = Stack([0; 4096 * 4 * NCPU]);
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#[no_mangle]
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pub unsafe fn rust_start() -> ! {
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// set MPP mode to Supervisor, for mret
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mstatus::set_mpp(mstatus::MPP::Supervisor);
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// set MEPC to main, for mret
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mepc::write(rust_main as usize);
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// disable paging for now.
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satp::write(0);
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// delegate all interrupts and exceptions to supervisor mode.
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medeleg::set_all();
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mideleg::set_all();
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sie::set_sext();
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sie::set_ssoft();
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sie::set_stimer();
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// configure Physical Memory Protection to give supervisor mode
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// access to all of physical memory.
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pmpaddr0::write(0x3fffffffffffff);
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pmpcfg0::set_pmp(0, Range::TOR, Permission::RWX, false); // 0 < addr < pmpaddr0
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// ask for clock interrupts.
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timerinit();
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// keep each CPU's hartid in its tp register, for cpuid().
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let id = mhartid::read();
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asm!("mv tp, {0}", in(reg) id);
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// switch to supervisor mode and jump to main().
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asm!("mret");
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extern "C" {
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fn rust_main() -> !;
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}
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unreachable_unchecked();
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}
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// a scratch area per CPU for machine-mode timer interrupts.
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static mut TIMER_SCRATCH: [[u64; 5]; 1] = [[0; 5]; 1];
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unsafe fn timerinit() {
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// each CPU has a separate source of timer interrupts
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let id = mhartid::read();
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// ask the CLINT for a timer interrupts
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let interval = 1000000u64; // cycles; about 1/10th second in qemu.
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let mtimecmp = clint_mtimecmp(id) as *mut u64;
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let mtime = CLINT_MTIME as *const u64;
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mtimecmp.write_volatile(mtime.read_volatile() + interval);
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// prepare information in scratch[] for timervec.
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// scratch[0..2] : space for timervec to save registers.
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// scratch[3] : address of CLINT MTIMECMP register.
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// scratch[4] : desired interval (in cycles) between timer interrupts.
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let scratch = &mut TIMER_SCRATCH[id];
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scratch[3] = mtimecmp as u64;
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scratch[4] = interval;
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mscratch::write(scratch.as_mut_ptr() as usize);
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// set the machine-mode trap handler
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mtvec::write(timervec as usize, mtvec::TrapMode::Direct);
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// enable machine-mode interrupts.
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mstatus::set_mie();
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// enable machime-mode timer interrupts.
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mie::set_mtimer();
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} |