From e71bbcbc8d2f51b89a0efe985be07e8966ffb211 Mon Sep 17 00:00:00 2001
From: Yu Chen <yuchen@mail.tsinghua.edu.cn>
Date: Tue, 3 Jan 2023 09:50:56 +0800
Subject: [PATCH] in gdb mode, OK. For the safety of TIMER_SCRATCH, put
 clear_bss Fn in rust_start. and explicitly UART.init in rust_main.

---
 os/src/drivers/chardev/mod.rs      |  1 +
 os/src/drivers/chardev/ns16550a.rs |  7 ++++++-
 os/src/main.rs                     | 17 +++++++++--------
 3 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/os/src/drivers/chardev/mod.rs b/os/src/drivers/chardev/mod.rs
index de1446d..64c168f 100644
--- a/os/src/drivers/chardev/mod.rs
+++ b/os/src/drivers/chardev/mod.rs
@@ -6,6 +6,7 @@ use lazy_static::*;
 pub use ns16550a::NS16550a;
 
 pub trait CharDevice {
+    fn init(&self);
     fn read(&self) -> u8;
     fn write(&self, ch: u8);
     fn handle_irq(&self);
diff --git a/os/src/drivers/chardev/ns16550a.rs b/os/src/drivers/chardev/ns16550a.rs
index da29063..de53b3e 100644
--- a/os/src/drivers/chardev/ns16550a.rs
+++ b/os/src/drivers/chardev/ns16550a.rs
@@ -135,7 +135,7 @@ impl<const BASE_ADDR: usize> NS16550a<BASE_ADDR> {
             ns16550a: NS16550aRaw::new(BASE_ADDR),
             read_buffer: VecDeque::new(),
         };
-        inner.ns16550a.init();
+        //inner.ns16550a.init();
         Self {
             inner: unsafe { UPIntrFreeCell::new(inner) },
             condvar: Condvar::new(),
@@ -144,6 +144,11 @@ impl<const BASE_ADDR: usize> NS16550a<BASE_ADDR> {
 }
 
 impl<const BASE_ADDR: usize> CharDevice for NS16550a<BASE_ADDR> {
+    fn init(&self){
+        let mut inner = self.inner.exclusive_access();
+        inner.ns16550a.init();
+        drop(inner);
+    }    
     fn read(&self) -> u8 {
         loop {
             let mut inner = self.inner.exclusive_access();
diff --git a/os/src/main.rs b/os/src/main.rs
index 56fba0c..4440253 100644
--- a/os/src/main.rs
+++ b/os/src/main.rs
@@ -214,6 +214,7 @@ pub unsafe fn mie_write(x:usize){
 }
 
 unsafe fn timer_init() {
+    clear_bss();
     // each CPU has a separate source of timer interrupts
     //let id = mhartid::read();
 
@@ -246,19 +247,19 @@ unsafe fn timer_init() {
     //mie::set_mtimer();
 }
 
-
+use crate::drivers::chardev::CharDevice;
+use crate::drivers::chardev::UART;
 #[no_mangle]
 pub fn rust_main() -> ! {
 
-    clear_bss();
-
-    println!("KERN: begin");
-
+    //clear_bss();
     mm::init();
+    UART.init();
+    println!("KERN: begin");
     //loop{};
-    //println!("KERN: init gpu");
-    //let _gpu = GPU_DEVICE.clone();
-   // println!("KERN: init keyboard");
+    println!("KERN: init gpu");
+    let _gpu = GPU_DEVICE.clone();
+    println!("KERN: init keyboard");
    // let _keyboard = KEYBOARD_DEVICE.clone();
     //println!("KERN: init mouse");
     //let _mouse = MOUSE_DEVICE.clone();