cargo fmt && use rustsbi as the bootl
This commit is contained in:
Yifan Wu
parent
099b9b2ddd
commit
45ab29ae1b
43 changed files with 545 additions and 1489 deletions
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@ -10,7 +10,6 @@ edition = "2021"
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riscv = { git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] }
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lazy_static = { version = "1.4.0", features = ["spin_no_std"] }
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buddy_system_allocator = "0.6"
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bit_field = "0.10.0"
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bitflags = "1.2.1"
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xmas-elf = "0.7.0"
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volatile = "0.3"
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14
os/Makefile
14
os/Makefile
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@ -24,7 +24,7 @@ ifeq ($(MODE), release)
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endif
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# KERNEL ENTRY
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KERNEL_ENTRY_PA := 0x80000000
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KERNEL_ENTRY_PA := 0x80200000
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# Binutils
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OBJDUMP := rust-objdump --arch-name=riscv64
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@ -109,18 +109,6 @@ fdt:
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@qemu-system-riscv64 -M 128m -machine virt,dumpdtb=virt.out
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fdtdump virt.out
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debug-none: build
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@tmux new-session -d \
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"qemu-system-riscv64 -machine virt -nographic -bios none -kernel $(KERNEL_ELF) \
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-drive file=$(FS_IMG),if=none,format=raw,id=x0 \
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-device virtio-blk-device,drive=x0 \
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-device virtio-keyboard-device \
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-device virtio-mouse-device \
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-serial stdio \
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-s -S" && \
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tmux split-window -h "riscv64-unknown-elf-gdb -ex 'file $(KERNEL_ELF)' -ex 'set arch riscv:rv64' -ex 'target remote localhost:1234'" && \
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tmux -2 attach-session -d
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debug: build
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@tmux new-session -d \
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"qemu-system-riscv64 -machine virt -nographic -bios $(BOOTLOADER) -device loader,file=$(KERNEL_BIN),addr=$(KERNEL_ENTRY_PA) -s -S" && \
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@ -2,9 +2,9 @@ pub const CLOCK_FREQ: usize = 12500000;
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pub const MMIO: &[(usize, usize)] = &[
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(0x0010_0000, 0x00_2000), // VIRT_TEST/RTC in virt machine
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(0x2000000, 0x10000), // core local interrupter (CLINT)
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(0xc000000, 0x210000), // VIRT_PLIC in virt machine
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(0x10000000, 0x9000), // VIRT_UART0 with GPU in virt machine
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(0x2000000, 0x10000), // core local interrupter (CLINT)
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(0xc000000, 0x210000), // VIRT_PLIC in virt machine
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(0x10000000, 0x9000), // VIRT_UART0 with GPU in virt machine
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];
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pub type BlockDeviceImpl = crate::drivers::block::VirtIOBlock;
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@ -52,54 +52,3 @@ pub fn irq_handler() {
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}
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plic.complete(0, IntrTargetPriority::Supervisor, intr_src_id);
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}
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// core local interrupter (CLINT), which contains the timer
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pub const CLINT: usize = 0x2000000;
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// pub const fn clint_mtimecmp(hartid: usize) -> usize {
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// CLINT + 0x4000 + 8 * hartid
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// }
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pub const CLINT_MTIME: usize = CLINT + 0xBFF8; // Cycles since boot.
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pub const CLINT_MTIMECMP: usize = CLINT + 0x4000;
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#[naked]
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#[repr(align(16))] // if miss this alignment, a load access fault will occur.
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#[no_mangle]
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pub unsafe extern "C" fn timervec() -> ! {
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// start.rs has set up the memory that mscratch points to:
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// scratch[0,8,16] : register save area.
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// scratch[24] : address of CLINT's MTIMECMP register.
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// scratch[32] : desired interval between interrupts.
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// Now, mscrach has a pointer to an additional scratch space.
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// to aboid overwriting the contents of the integer registers,
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// the prologue of an interrupts handler usually begins by swapping
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// an integer register(say a0) with mscratch CSR.
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// The interrupt handler stores the integer registers
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// used for processing in this scratch space.
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// a0 saved in mscrach, a1 ~ a3 saved in scratch space.
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//loop {}
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core::arch::asm!(
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"csrrw a0, mscratch, a0",
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"sd a1, 0(a0)",
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"sd a2, 8(a0)",
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"sd a3, 16(a0)",
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// schedule the next timer interrupt
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// by adding interval to mtimecmp.
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"ld a1, 24(a0)", // CLINT_MTIMECMP(hartid) contents
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"ld a2, 32(a0)", // interval
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"ld a3, 0(a1)",
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"add a3, a3, a2",
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"sd a3, 0(a1)",
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// raise a supervisor software interrupt.
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"li a1, 2",
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"csrw sip, a1",
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// restore and return
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"ld a3, 16(a0)",
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"ld a2, 8(a0)",
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"ld a1, 0(a0)",
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"csrrw a0, mscratch, a0",
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"mret",
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options(noreturn)
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);
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}
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@ -1,10 +1,10 @@
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use super::BlockDevice;
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use crate::drivers::bus::virtio::VirtioHal;
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use crate::sync::{Condvar, UPIntrFreeCell};
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use crate::task::schedule;
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use crate::DEV_NON_BLOCKING_ACCESS;
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use alloc::collections::BTreeMap;
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use virtio_drivers::{BlkResp, RespStatus, VirtIOBlk, VirtIOHeader};
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use crate::drivers::bus::virtio::VirtioHal;
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#[allow(unused)]
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const VIRTIO0: usize = 0x10008000;
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@ -1,10 +1,10 @@
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use crate::drivers::bus::virtio::VirtioHal;
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use crate::sync::UPIntrFreeCell;
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use alloc::{sync::Arc, vec::Vec};
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use core::any::Any;
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use embedded_graphics::pixelcolor::Rgb888;
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use tinybmp::Bmp;
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use virtio_drivers::{VirtIOGpu, VirtIOHeader};
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use crate::drivers::bus::virtio::VirtioHal;
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const VIRTIO7: usize = 0x10007000;
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pub trait GpuDevice: Send + Sync + Any {
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fn update_cursor(&self);
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@ -2,7 +2,7 @@
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.globl _start
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_start:
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la sp, boot_stack_top
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call rust_start
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call rust_main
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.section .bss.stack
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.globl boot_stack_lower_bound
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@ -1,6 +1,6 @@
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OUTPUT_ARCH(riscv)
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ENTRY(_start)
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BASE_ADDRESS = 0x80000000;
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BASE_ADDRESS = 0x80200000;
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SECTIONS
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{
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210
os/src/main.rs
210
os/src/main.rs
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@ -2,8 +2,6 @@
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#![no_main]
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#![feature(panic_info_message)]
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#![feature(alloc_error_handler)]
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#![feature(naked_functions)]
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#![feature(fn_align)]
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//use crate::drivers::{GPU_DEVICE, KEYBOARD_DEVICE, MOUSE_DEVICE, INPUT_CONDVAR};
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use crate::drivers::{GPU_DEVICE, KEYBOARD_DEVICE, MOUSE_DEVICE};
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@ -14,7 +12,7 @@ extern crate bitflags;
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#[path = "boards/qemu.rs"]
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mod board;
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use board::*;
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#[macro_use]
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mod console;
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mod config;
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@ -30,15 +28,8 @@ mod task;
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mod timer;
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mod trap;
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use riscv::register::*;
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// mod riscvreg;
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// use riscvreg::{
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// mstatus, mepc, satp, medeleg, mideleg, sie, mhartid, tp, clint,
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// mscratch, mtvec, mie, sstatus
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// };
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// use riscvregs::registers::*;
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// use riscvregs::registers::pmpcfg0::*;
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//use syscall::create_desktop; //for test
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use crate::drivers::chardev::CharDevice;
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use crate::drivers::chardev::UART;
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core::arch::global_asm!(include_str!("entry.asm"));
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@ -61,198 +52,9 @@ lazy_static! {
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unsafe { UPIntrFreeCell::new(false) };
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}
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#[repr(C, align(16))]
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struct Stack([u8; 4096 * 4 * 1]);
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#[no_mangle]
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static mut STACK0: Stack = Stack([0; 4096 * 4 * 1]);
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#[inline]
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pub unsafe fn medeleg_write(medeleg: usize){
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core::arch::asm!("csrw medeleg, {}",in(reg)medeleg);
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}
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pub unsafe fn mideleg_write(mideleg: usize) {
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core::arch::asm!("csrw mideleg, {}", in(reg)mideleg);
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}
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pub enum SIE {
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SEIE = 1 << 9, // external
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STIE = 1 << 5, // timer
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SSIE = 1 << 1, // software
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}
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#[inline]
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pub unsafe fn sie_read() -> usize {
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let ret:usize;
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core::arch::asm!("csrr {}, sie", out(reg)ret);
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ret
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}
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#[inline]
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pub unsafe fn sie_write(x:usize) {
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core::arch::asm!("csrw sie, {}", in(reg)x);
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}
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/// enable all software interrupts
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/// still need to set SIE bit in sstatus
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pub unsafe fn intr_on() {
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let mut sie = sie_read();
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sie |= SIE::SSIE as usize | SIE::STIE as usize | SIE::SEIE as usize;
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sie_write(sie);
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}
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#[no_mangle]
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pub unsafe fn rust_start() -> ! {
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// set MPP mode to Supervisor, for mret
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mstatus::set_mpp(mstatus::MPP::Supervisor);
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// set MEPC to main, for mret
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mepc::write(rust_main as usize);
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// disable paging for now.
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satp::write(0);
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// delegate all interrupts and exceptions to supervisor mode.
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medeleg_write(0xffff);
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mideleg_write(0xffff);
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intr_on();
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// configure Physical Memory Protection to give supervisor mode
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// access to all of physical memory.
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pmpaddr0::write(0x3fffffffffffff);
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pmpcfg0::write(0xf);
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//pmpcfg0::set_pmp(0, Range::TOR, Permission::RWX, false); // 0 < addr < pmpaddr0
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// ask for clock interrupts.
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timer_init();
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// keep each CPU's hartid in its tp register, for cpuid().
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// let id = mhartid::read();
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// core::arch::asm!("mv tp, {0}", in(reg) id);
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// switch to supervisor mode and jump to main().
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core::arch::asm!("mret");
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extern "C" {
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fn rust_main() -> !;
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}
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core::hint::unreachable_unchecked();
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}
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use core::convert::Into;
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use core::ptr;
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// a scratch area per CPU for machine-mode timer interrupts.
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static mut TIMER_SCRATCH: [u64; 5] = [0; 5];
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#[inline]
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unsafe fn read_mtime() -> u64 {
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ptr::read_volatile(Into::<usize>::into(CLINT_MTIME) as *const u64)
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}
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unsafe fn write_mtimecmp(value: u64) {
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let offset = Into::<usize>::into(CLINT_MTIMECMP);
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ptr::write_volatile(offset as *mut u64, value);
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}
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pub unsafe fn add_mtimecmp(interval:u64){
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let value = read_mtime();
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write_mtimecmp(value+interval);
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}
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pub fn count_mtiecmp() -> usize{
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let ret:usize;
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ret = Into::<usize>::into(CLINT) + 0x4000;
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ret
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}
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#[inline]
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pub unsafe fn mtvec_write(x:usize){
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core::arch::asm!("csrw mtvec, {}",in(reg)x);
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}
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use bit_field::BitField;
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#[inline]
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unsafe fn mstatus_read() -> usize {
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let ret:usize;
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core::arch::asm!("csrr {}, mstatus",out(reg)ret);
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ret
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}
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#[inline]
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unsafe fn mstatus_write(x: usize) {
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core::arch::asm!("csrw mstatus, {}",in(reg)x);
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}
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// enable machine-mode interrupts.
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pub unsafe fn mstatus_enable_interrupt(){
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let mut mstatus = mstatus_read();
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mstatus.set_bit(3, true);
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mstatus_write(mstatus);
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}
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pub enum MIE {
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MEIE = 1 << 11, // external
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MTIE = 1 << 7, // timer
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MSIE = 1 << 3 // software
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}
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#[inline]
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pub unsafe fn mie_read() -> usize {
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let ret:usize;
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core::arch::asm!("csrr {}, mie", out(reg)ret);
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ret
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}
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#[inline]
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pub unsafe fn mie_write(x:usize){
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core::arch::asm!("csrw mie, {}",in(reg)x);
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}
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unsafe fn timer_init() {
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clear_bss();
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// each CPU has a separate source of timer interrupts
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//let id = mhartid::read();
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// ask the CLINT for a timer interrupts
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let interval = 1000000u64; // cycles; about 1/10th second in qemu.
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add_mtimecmp(interval);
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// let mtimecmp = board::clint_mtimecmp(0) as *mut u64;
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// let mtime = board::CLINT_MTIME as *const u64;
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// mtimecmp.write_volatile(mtime.read_volatile() + interval);
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// prepare information in scratch[] for timervec.
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// scratch[0..2] : space for timervec to save registers.
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// scratch[3] : address of CLINT MTIMECMP register.
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// scratch[4] : desired interval (in cycles) between timer interrupts.
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let scratch = &mut TIMER_SCRATCH;
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scratch[3] = count_mtiecmp() as u64;
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scratch[4] = interval;
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mscratch::write(scratch.as_mut_ptr() as usize);
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// set the machine-mode trap handler
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mtvec_write(timervec as usize);
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//mtvec::write(board::timervec as usize, mtvec::TrapMode::Direct);
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// enable machine-mode interrupts.
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mstatus_enable_interrupt();
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//mstatus::set_mie();
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// enable machine-mode timer interrupts.
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mie_write(mie_read() | MIE::MTIE as usize);
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//mie::set_mtimer();
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}
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use crate::drivers::chardev::CharDevice;
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use crate::drivers::chardev::UART;
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#[no_mangle]
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pub fn rust_main() -> ! {
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//clear_bss();
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clear_bss();
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mm::init();
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UART.init();
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println!("KERN: init gpu");
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@ -263,8 +65,8 @@ pub fn rust_main() -> ! {
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let _mouse = MOUSE_DEVICE.clone();
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println!("KERN: init trap");
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trap::init();
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//trap::enable_timer_interrupt();
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//timer::set_next_trigger();
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trap::enable_timer_interrupt();
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timer::set_next_trigger();
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board::device_init();
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fs::list_apps();
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task::add_initproc();
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@ -75,7 +75,7 @@ impl FrameAllocator for StackFrameAllocator {
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None
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} else {
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self.current += pages;
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let arr:Vec<usize> = (1..pages + 1).collect();
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let arr: Vec<usize> = (1..pages + 1).collect();
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let v = arr.iter().map(|x| (self.current - x).into()).collect();
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Some(v)
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}
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@ -144,7 +144,6 @@ pub fn frame_allocator_test() {
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println!("frame_allocator_test passed!");
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}
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#[allow(unused)]
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pub fn frame_allocator_alloc_more_test() {
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let mut v: Vec<FrameTracker> = Vec::new();
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@ -1,7 +1,7 @@
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pub mod port_table;
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pub mod socket;
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pub mod tcp;
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pub mod udp;
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pub mod port_table;
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pub use lose_net_stack::IPv4;
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@ -95,7 +95,7 @@ pub fn net_interrupt_handler() {
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if let Some(socket_index) = get_socket(target, lport, rport) {
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push_data(socket_index, tcp_packet.data.to_vec());
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set_s_a_by_index(socket_index, tcp_packet.seq, tcp_packet.ack);
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}
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}
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}
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_ => {}
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}
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@ -1,4 +1,4 @@
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use alloc::{vec::Vec, sync::Arc};
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use alloc::{sync::Arc, vec::Vec};
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use lazy_static::lazy_static;
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use lose_net_stack::packets::tcp::TCPPacket;
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@ -11,7 +11,7 @@ use super::tcp::TCP;
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pub struct Port {
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pub port: u16,
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pub receivable: bool,
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pub schedule: Option<Arc<TaskControlBlock>>
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pub schedule: Option<Arc<TaskControlBlock>>,
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}
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||||
|
||||
lazy_static! {
|
||||
|
|
@ -32,7 +32,7 @@ pub fn listen(port: u16) -> Option<usize> {
|
|||
let listen_port = Port {
|
||||
port,
|
||||
receivable: false,
|
||||
schedule: None
|
||||
schedule: None,
|
||||
};
|
||||
|
||||
if index == usize::MAX {
|
||||
|
|
@ -66,10 +66,13 @@ pub fn port_acceptable(listen_index: usize) -> bool {
|
|||
// check whether it can accept request
|
||||
pub fn check_accept(port: u16, tcp_packet: &TCPPacket) -> Option<()> {
|
||||
LISTEN_TABLE.exclusive_session(|listen_table| {
|
||||
let mut listen_ports: Vec<&mut Option<Port>> = listen_table.iter_mut().filter(|x| match x {
|
||||
Some(t) => t.port == port && t.receivable == true,
|
||||
None => false,
|
||||
}).collect();
|
||||
let mut listen_ports: Vec<&mut Option<Port>> = listen_table
|
||||
.iter_mut()
|
||||
.filter(|x| match x {
|
||||
Some(t) => t.port == port && t.receivable == true,
|
||||
None => false,
|
||||
})
|
||||
.collect();
|
||||
if listen_ports.len() == 0 {
|
||||
None
|
||||
} else {
|
||||
|
|
@ -90,7 +93,13 @@ pub fn accept_connection(_port: u16, tcp_packet: &TCPPacket, task: Arc<TaskContr
|
|||
let mut inner = process.inner_exclusive_access();
|
||||
let fd = inner.alloc_fd();
|
||||
|
||||
let tcp_socket = TCP::new(tcp_packet.source_ip, tcp_packet.dest_port, tcp_packet.source_port, tcp_packet.seq, tcp_packet.ack);
|
||||
let tcp_socket = TCP::new(
|
||||
tcp_packet.source_ip,
|
||||
tcp_packet.dest_port,
|
||||
tcp_packet.source_port,
|
||||
tcp_packet.seq,
|
||||
tcp_packet.ack,
|
||||
);
|
||||
|
||||
inner.fd_table[fd] = Some(Arc::new(tcp_socket));
|
||||
|
||||
|
|
@ -130,4 +139,3 @@ impl File for PortFd {
|
|||
0
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ pub struct Socket {
|
|||
pub rport: u16, // rempote port
|
||||
pub buffers: VecDeque<Vec<u8>>, // datas
|
||||
pub seq: u32,
|
||||
pub ack: u32
|
||||
pub ack: u32,
|
||||
}
|
||||
|
||||
lazy_static! {
|
||||
|
|
@ -26,11 +26,9 @@ pub fn get_s_a_by_index(index: usize) -> Option<(u32, u32)> {
|
|||
|
||||
assert!(index < socket_table.len());
|
||||
|
||||
socket_table.get(index).map_or(None, |x| {
|
||||
match x {
|
||||
Some(x) => Some((x.seq, x.ack)),
|
||||
None => None,
|
||||
}
|
||||
socket_table.get(index).map_or(None, |x| match x {
|
||||
Some(x) => Some((x.seq, x.ack)),
|
||||
None => None,
|
||||
})
|
||||
}
|
||||
|
||||
|
|
@ -40,9 +38,7 @@ pub fn set_s_a_by_index(index: usize, seq: u32, ack: u32) {
|
|||
assert!(socket_table.len() > index);
|
||||
assert!(socket_table[index].is_some());
|
||||
|
||||
let sock = socket_table[index]
|
||||
.as_mut()
|
||||
.unwrap();
|
||||
let sock = socket_table[index].as_mut().unwrap();
|
||||
|
||||
sock.ack = ack;
|
||||
sock.seq = seq;
|
||||
|
|
@ -84,7 +80,7 @@ pub fn add_socket(raddr: IPv4, lport: u16, rport: u16) -> Option<usize> {
|
|||
rport,
|
||||
buffers: VecDeque::new(),
|
||||
seq: 0,
|
||||
ack: 0
|
||||
ack: 0,
|
||||
};
|
||||
|
||||
if index == usize::MAX {
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
use alloc::vec;
|
||||
use lose_net_stack::MacAddress;
|
||||
use lose_net_stack::IPv4;
|
||||
use lose_net_stack::TcpFlags;
|
||||
use lose_net_stack::packets::tcp::TCPPacket;
|
||||
use lose_net_stack::IPv4;
|
||||
use lose_net_stack::MacAddress;
|
||||
use lose_net_stack::TcpFlags;
|
||||
|
||||
use crate::{drivers::NET_DEVICE, fs::File};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,614 +0,0 @@
|
|||
// RISC-V registers
|
||||
pub mod registers {
|
||||
// hart (core) id registers
|
||||
pub mod mhartid {
|
||||
use core::arch::asm;
|
||||
|
||||
#[inline]
|
||||
pub fn read() -> usize {
|
||||
let id: usize;
|
||||
unsafe {
|
||||
asm!("csrr {}, mhartid", out(reg) id);
|
||||
}
|
||||
id
|
||||
}
|
||||
}
|
||||
|
||||
// Machine Status Register, mstatus
|
||||
pub mod mstatus {
|
||||
use core::arch::asm;
|
||||
|
||||
// Machine Status Register bit
|
||||
const MPP_MASK: usize = 3 << 11;
|
||||
const MIE: usize = 1 << 3;
|
||||
|
||||
// Machine Previous Privilege mode
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum MPP {
|
||||
Machine = 3,
|
||||
Supervisor = 1,
|
||||
User = 0,
|
||||
}
|
||||
|
||||
#[inline]
|
||||
unsafe fn _read() -> usize {
|
||||
let bits: usize;
|
||||
asm!("csrr {}, mstatus", out(reg) bits);
|
||||
bits
|
||||
}
|
||||
|
||||
#[inline]
|
||||
unsafe fn _write(bits: usize) {
|
||||
asm!("csrw mstatus, {}", in(reg) bits);
|
||||
}
|
||||
|
||||
// Machine Previous Privilege Mode
|
||||
#[inline]
|
||||
pub fn set_mpp(mpp: MPP) {
|
||||
unsafe {
|
||||
let mut value = _read();
|
||||
value &= !MPP_MASK;
|
||||
value |= (mpp as usize) << 11;
|
||||
_write(value);
|
||||
}
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn set_mie() {
|
||||
unsafe {
|
||||
asm!("csrs mstatus, {}", in(reg) MIE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// machine exception program counter, holds the
|
||||
// instruction address to which a return from
|
||||
// exception will go.
|
||||
pub mod mepc {
|
||||
use core::arch::asm;
|
||||
|
||||
#[inline]
|
||||
pub fn write(x: usize) {
|
||||
unsafe {
|
||||
asm!("csrw mepc, {}", in(reg) x);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Supervisor Status Register, sstatus
|
||||
pub mod sstatus {
|
||||
use core::arch::asm;
|
||||
|
||||
// Supervisor Status Register bit
|
||||
const SPP: usize = 1 << 8; // Previous mode, 1=Supervisor, 0=user
|
||||
const SPIE: usize = 1 << 5; // Supervisor Previous Interrupt Enable
|
||||
const SIE: usize = 1 << 1; // Supervisor Interrupt Enable
|
||||
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub struct Sstatus {
|
||||
bits: usize,
|
||||
}
|
||||
|
||||
impl Sstatus {
|
||||
// Supervisor Interrupt Enable
|
||||
#[inline]
|
||||
pub(in crate::riscvregs) fn sie(&self) -> bool {
|
||||
self.bits & SIE != 0
|
||||
}
|
||||
|
||||
// Supervisor Previous Privilege mode
|
||||
#[inline]
|
||||
pub fn spp(&self) -> SPP {
|
||||
match self.bits & SPP {
|
||||
0 => SPP::User,
|
||||
_ => SPP::Supervisor,
|
||||
}
|
||||
}
|
||||
|
||||
// restore status bits
|
||||
#[inline]
|
||||
pub fn restore(&self) {
|
||||
unsafe {
|
||||
_write(self.bits);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Supervisor Previous Privilege Mode
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum SPP {
|
||||
Supervisor = 1,
|
||||
User = 0,
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn read() -> Sstatus {
|
||||
let bits: usize;
|
||||
unsafe { asm!("csrr {}, sstatus", out(reg) bits) }
|
||||
Sstatus { bits }
|
||||
}
|
||||
|
||||
#[inline]
|
||||
unsafe fn _write(bits: usize) {
|
||||
asm!("csrw sstatus, {}", in(reg) bits);
|
||||
}
|
||||
|
||||
// bit set
|
||||
#[inline]
|
||||
unsafe fn _set(bits: usize) {
|
||||
asm!("csrs sstatus, {}", in(reg) bits);
|
||||
}
|
||||
|
||||
// bit clear
|
||||
#[inline]
|
||||
unsafe fn _clear(bits: usize) {
|
||||
asm!("csrc sstatus, {}", in(reg) bits);
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub(in crate::riscvregs) unsafe fn set_sie() {
|
||||
_set(SIE)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub(in crate::riscvregs) unsafe fn clear_sie() {
|
||||
_clear(SIE)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn set_spie() {
|
||||
_set(SPIE);
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn set_spp(spp: SPP) {
|
||||
match spp {
|
||||
SPP::Supervisor => _set(SPP),
|
||||
SPP::User => _clear(SPP),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Supervisor Interrupt Pending
|
||||
pub mod sip {
|
||||
use core::arch::asm;
|
||||
|
||||
const SSIP: usize = 1 << 1;
|
||||
|
||||
// Supervisor Software Interrupt Pending
|
||||
#[inline]
|
||||
pub unsafe fn clear_ssoft() {
|
||||
asm!("csrc sip, {}", in(reg) SSIP);
|
||||
}
|
||||
}
|
||||
|
||||
// Supervisor Interrupt Enable
|
||||
pub mod sie {
|
||||
use core::arch::asm;
|
||||
|
||||
const SEIE: usize = 1 << 9; // external
|
||||
const STIE: usize = 1 << 5; // timer
|
||||
const SSIE: usize = 1 << 1; // software
|
||||
|
||||
#[inline]
|
||||
unsafe fn _set(bits: usize) {
|
||||
asm!("csrs sie, {}", in(reg) bits);
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn set_sext() {
|
||||
_set(SEIE);
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn set_stimer() {
|
||||
_set(STIE);
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn set_ssoft() {
|
||||
_set(SSIE);
|
||||
}
|
||||
}
|
||||
|
||||
// Machine-mode Interrupt Enable
|
||||
pub mod mie {
|
||||
use core::arch::asm;
|
||||
|
||||
const MTIE: usize = 1 << 7;
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn set_mtimer() {
|
||||
asm!("csrs mie, {}", in(reg) MTIE);
|
||||
}
|
||||
}
|
||||
|
||||
// supervisor exceptions program counter, holds the
|
||||
// instruction address to which a return from
|
||||
// exception will go.
|
||||
pub mod sepc {
|
||||
use core::arch::asm;
|
||||
|
||||
#[inline]
|
||||
pub fn read() -> usize {
|
||||
let bits: usize;
|
||||
unsafe {
|
||||
asm!("csrr {}, sepc", out(reg) bits);
|
||||
}
|
||||
bits
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn write(bits: usize) {
|
||||
unsafe {
|
||||
asm!("csrw sepc, {}", in(reg) bits);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Machine Exception Delegation
|
||||
pub mod medeleg {
|
||||
use core::arch::asm;
|
||||
|
||||
pub unsafe fn set_all() {
|
||||
asm!("csrw medeleg, {}", in(reg) 0xffff);
|
||||
}
|
||||
}
|
||||
|
||||
// Machine Interrupt Delegation
|
||||
pub mod mideleg {
|
||||
use core::arch::asm;
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn set_all() {
|
||||
asm!("csrw mideleg, {}", in(reg) 0xffff);
|
||||
}
|
||||
}
|
||||
|
||||
// Supervisor Trap-Vector Base Address
|
||||
// low two bits are mode.
|
||||
pub mod stvec {
|
||||
pub use super::mtvec::TrapMode;
|
||||
use core::arch::asm;
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn write(addr: usize, mode: TrapMode) {
|
||||
asm!("csrw stvec, {}", in(reg) addr + mode as usize);
|
||||
}
|
||||
}
|
||||
|
||||
// Machine-mode interrupt vector
|
||||
pub mod mtvec {
|
||||
use core::arch::asm;
|
||||
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum TrapMode {
|
||||
Direct = 0,
|
||||
Vectored = 1,
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn write(addr: usize, mode: TrapMode) {
|
||||
asm!("csrw mtvec, {}", in(reg) addr + mode as usize);
|
||||
}
|
||||
}
|
||||
|
||||
// Physical Memory Protection Configuration
|
||||
pub mod pmpcfg0 {
|
||||
use core::arch::asm;
|
||||
|
||||
// Permission enum contains all possible permission modes for pmp registers
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub enum Permission {
|
||||
NONE = 0b000,
|
||||
R = 0b001,
|
||||
W = 0b010,
|
||||
RW = 0b011,
|
||||
X = 0b100,
|
||||
RX = 0b101,
|
||||
WX = 0b110,
|
||||
RWX = 0b111,
|
||||
}
|
||||
|
||||
// Range enum contains all possible addressing modes for pmp registers
|
||||
pub enum Range {
|
||||
OFF = 0b00,
|
||||
TOR = 0b01,
|
||||
NA4 = 0b10,
|
||||
NAPOT = 0b11,
|
||||
}
|
||||
|
||||
// Set the pmp configuration corresponging to the index
|
||||
#[inline]
|
||||
pub unsafe fn set_pmp(index: usize, range: Range, permission: Permission, locked: bool) {
|
||||
assert!(index < 8);
|
||||
let mut value = _read();
|
||||
let byte = (locked as usize) << 7 | (range as usize) << 3 | (permission as usize);
|
||||
value |= byte << (8 * index);
|
||||
_write(value);
|
||||
}
|
||||
|
||||
#[inline]
|
||||
unsafe fn _read() -> usize {
|
||||
let bits: usize;
|
||||
asm!("csrr {}, pmpcfg0", out(reg) bits);
|
||||
bits
|
||||
}
|
||||
|
||||
#[inline]
|
||||
unsafe fn _write(bits: usize) {
|
||||
asm!("csrw pmpcfg0, {}", in(reg) bits);
|
||||
}
|
||||
}
|
||||
|
||||
// Physical memory protection address register
|
||||
pub mod pmpaddr0 {
|
||||
use core::arch::asm;
|
||||
|
||||
pub fn write(bits: usize) {
|
||||
unsafe {
|
||||
asm!("csrw pmpaddr0, {}", in(reg) bits);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Supervisor address translation and protection;
|
||||
// holds the address of the page table.
|
||||
pub mod satp {
|
||||
use core::arch::asm;
|
||||
|
||||
// stap register
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub struct Satp {
|
||||
bits: usize,
|
||||
}
|
||||
|
||||
// 64-bit satp mode
|
||||
pub enum Mode {
|
||||
// No translation or protection
|
||||
Bare = 0,
|
||||
// Page-based 39-bit virtual addressing
|
||||
Sv39 = 8,
|
||||
// Page-based 48-bit virtual addressing
|
||||
Sv48 = 9,
|
||||
// Page-based 57-bit virtual addressing
|
||||
Sv57 = 10,
|
||||
// Page-based 64-bit virtual addressing
|
||||
Sv64 = 11,
|
||||
}
|
||||
|
||||
impl Satp {
|
||||
// Return the contents of the register as raw bits
|
||||
#[inline]
|
||||
pub fn bits(&self) -> usize {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn read() -> Satp {
|
||||
let bits: usize;
|
||||
asm!("csrr {}, satp", out(reg) bits);
|
||||
Satp { bits }
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub unsafe fn write(bits: usize) {
|
||||
asm!("csrw satp, {}", in(reg) bits);
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn make(mode: Mode, asid: usize, ppn: usize) -> usize {
|
||||
let mut bits: usize = 0;
|
||||
bits |= (mode as usize) << 60;
|
||||
bits |= asid << 44;
|
||||
bits |= ppn >> 12;
|
||||
bits
|
||||
}
|
||||
}
|
||||
|
||||
// mscratch register
|
||||
pub mod mscratch {
|
||||
use core::arch::asm;
|
||||
|
||||
#[inline]
|
||||
pub fn write(bits: usize) {
|
||||
unsafe {
|
||||
asm!("csrw mscratch, {}", in(reg) bits);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Supervisor Trap Cause
|
||||
pub mod scause {
|
||||
use core::{arch::asm, mem::size_of};
|
||||
|
||||
// scause register
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct Scause {
|
||||
bits: usize,
|
||||
}
|
||||
|
||||
// Trap Cause
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum Trap {
|
||||
Interrupt(Interrupt),
|
||||
Exception(Exception),
|
||||
}
|
||||
|
||||
// Interrupt
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum Interrupt {
|
||||
UserSoft,
|
||||
SupervisorSoft,
|
||||
UserTimer,
|
||||
SupervisorTimer,
|
||||
UserExternal,
|
||||
SupervisorExternal,
|
||||
Unknown,
|
||||
}
|
||||
|
||||
// Exception
|
||||
#[derive(Copy, Clone, Debug, Eq, PartialEq)]
|
||||
pub enum Exception {
|
||||
InstructionMisaligned,
|
||||
InstructionFault,
|
||||
IllegalInstruction,
|
||||
Breakpoint,
|
||||
LoadFault,
|
||||
StoreMisaligned,
|
||||
StoreFault,
|
||||
UserEnvCall,
|
||||
InstructionPageFault,
|
||||
LoadPageFault,
|
||||
StorePageFault,
|
||||
Unknown,
|
||||
}
|
||||
|
||||
impl Interrupt {
|
||||
#[inline]
|
||||
pub fn from(nr: usize) -> Self {
|
||||
match nr {
|
||||
0 => Interrupt::UserSoft,
|
||||
1 => Interrupt::SupervisorSoft,
|
||||
4 => Interrupt::UserTimer,
|
||||
5 => Interrupt::SupervisorTimer,
|
||||
8 => Interrupt::UserExternal,
|
||||
9 => Interrupt::SupervisorExternal,
|
||||
_ => Interrupt::Unknown,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Exception {
|
||||
#[inline]
|
||||
pub fn from(nr: usize) -> Self {
|
||||
match nr {
|
||||
0 => Exception::InstructionMisaligned,
|
||||
1 => Exception::InstructionFault,
|
||||
2 => Exception::IllegalInstruction,
|
||||
3 => Exception::Breakpoint,
|
||||
5 => Exception::LoadFault,
|
||||
6 => Exception::StoreMisaligned,
|
||||
7 => Exception::StoreFault,
|
||||
8 => Exception::UserEnvCall,
|
||||
12 => Exception::InstructionPageFault,
|
||||
13 => Exception::LoadPageFault,
|
||||
15 => Exception::StorePageFault,
|
||||
_ => Exception::Unknown,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Scause {
|
||||
// Returns the contents of the register as raw bits
|
||||
#[inline]
|
||||
pub fn bits(&self) -> usize {
|
||||
self.bits
|
||||
}
|
||||
|
||||
// Returns the code field
|
||||
#[inline]
|
||||
pub fn code(&self) -> usize {
|
||||
let bit = 1 << (size_of::<usize>() * 8 - 1);
|
||||
self.bits & !bit
|
||||
}
|
||||
|
||||
// Trap cause
|
||||
#[inline]
|
||||
pub fn cause(&self) -> Trap {
|
||||
if self.is_interrupt() {
|
||||
Trap::Interrupt(Interrupt::from(self.code()))
|
||||
} else {
|
||||
Trap::Exception(Exception::from(self.code()))
|
||||
}
|
||||
}
|
||||
|
||||
// Is trap cause an interrupt.
|
||||
#[inline]
|
||||
pub fn is_interrupt(&self) -> bool {
|
||||
self.bits & (1 << (size_of::<usize>() * 8 - 1)) != 0
|
||||
}
|
||||
|
||||
// Is trap cause an exception.
|
||||
#[inline]
|
||||
pub fn is_exception(&self) -> bool {
|
||||
!self.is_interrupt()
|
||||
}
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn read() -> Scause {
|
||||
let bits: usize;
|
||||
unsafe {
|
||||
asm!("csrr {}, scause", out(reg) bits);
|
||||
}
|
||||
Scause { bits }
|
||||
}
|
||||
}
|
||||
|
||||
// Supervisor Trap Value
|
||||
pub mod stval {
|
||||
use core::arch::asm;
|
||||
|
||||
#[inline]
|
||||
pub fn read() -> usize {
|
||||
let bits: usize;
|
||||
unsafe { asm!("csrr {}, stval", out(reg) bits) }
|
||||
bits
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
use core::arch::asm;
|
||||
|
||||
use registers::*;
|
||||
|
||||
// enable device interrupts
|
||||
#[inline]
|
||||
pub fn intr_on() {
|
||||
unsafe {
|
||||
sstatus::set_sie();
|
||||
}
|
||||
}
|
||||
|
||||
// disable device interrupts
|
||||
#[inline]
|
||||
pub fn intr_off() {
|
||||
unsafe {
|
||||
sstatus::clear_sie();
|
||||
}
|
||||
}
|
||||
|
||||
// are device interrupts enabled?
|
||||
#[inline]
|
||||
pub fn intr_get() -> bool {
|
||||
sstatus::read().sie()
|
||||
}
|
||||
|
||||
// flush the TLB.
|
||||
#[inline]
|
||||
pub unsafe fn sfence_vma() {
|
||||
// the zero, zero means flush all TLB entries
|
||||
asm!("sfence.vma zero, zero");
|
||||
}
|
||||
|
||||
pub const PGSIZE: usize = 4096; // bytes per page
|
||||
pub const PGSHIFT: usize = 12; // bits of offset within a page
|
||||
|
||||
pub const fn pgroundup(sz: usize) -> usize {
|
||||
(sz + PGSIZE - 1) & !(PGSIZE - 1)
|
||||
}
|
||||
|
||||
pub const fn pgrounddown(sz: usize) -> usize {
|
||||
sz & !(PGSIZE - 1)
|
||||
}
|
||||
|
||||
// PTE flags
|
||||
pub mod pteflags {
|
||||
pub const PTE_V: usize = 1 << 0; // valid
|
||||
pub const PTE_R: usize = 1 << 1;
|
||||
pub const PTE_W: usize = 1 << 2;
|
||||
pub const PTE_X: usize = 1 << 3;
|
||||
pub const PTE_U: usize = 1 << 4; // user can access
|
||||
}
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
//use crate::kernelvec::*;
|
||||
//use crate::memlayout::*;
|
||||
//use crate::param::NCPU;
|
||||
//use super::main::*;
|
||||
//use crate::riscv::registers::{pmpcfg0::*, *};
|
||||
use core::arch::asm;
|
||||
use core::hint::unreachable_unchecked;
|
||||
|
||||
mod riscv;
|
||||
|
||||
#[repr(C, align(16))]
|
||||
struct Stack([u8; 4096 * 4 * NCPU]);
|
||||
|
||||
#[no_mangle]
|
||||
static mut STACK0: Stack = Stack([0; 4096 * 4 * NCPU]);
|
||||
|
||||
#[no_mangle]
|
||||
pub unsafe fn rust_start() -> ! {
|
||||
// set MPP mode to Supervisor, for mret
|
||||
mstatus::set_mpp(mstatus::MPP::Supervisor);
|
||||
|
||||
// set MEPC to main, for mret
|
||||
mepc::write(rust_main as usize);
|
||||
|
||||
// disable paging for now.
|
||||
satp::write(0);
|
||||
|
||||
// delegate all interrupts and exceptions to supervisor mode.
|
||||
medeleg::set_all();
|
||||
mideleg::set_all();
|
||||
sie::set_sext();
|
||||
sie::set_ssoft();
|
||||
sie::set_stimer();
|
||||
|
||||
// configure Physical Memory Protection to give supervisor mode
|
||||
// access to all of physical memory.
|
||||
pmpaddr0::write(0x3fffffffffffff);
|
||||
pmpcfg0::set_pmp(0, Range::TOR, Permission::RWX, false); // 0 < addr < pmpaddr0
|
||||
|
||||
// ask for clock interrupts.
|
||||
timerinit();
|
||||
|
||||
// keep each CPU's hartid in its tp register, for cpuid().
|
||||
let id = mhartid::read();
|
||||
asm!("mv tp, {0}", in(reg) id);
|
||||
|
||||
// switch to supervisor mode and jump to main().
|
||||
asm!("mret");
|
||||
|
||||
extern "C" {
|
||||
fn rust_main() -> !;
|
||||
}
|
||||
unreachable_unchecked();
|
||||
}
|
||||
|
||||
// a scratch area per CPU for machine-mode timer interrupts.
|
||||
static mut TIMER_SCRATCH: [[u64; 5]; 1] = [[0; 5]; 1];
|
||||
|
||||
unsafe fn timerinit() {
|
||||
// each CPU has a separate source of timer interrupts
|
||||
let id = mhartid::read();
|
||||
|
||||
// ask the CLINT for a timer interrupts
|
||||
let interval = 1000000u64; // cycles; about 1/10th second in qemu.
|
||||
let mtimecmp = clint_mtimecmp(id) as *mut u64;
|
||||
let mtime = CLINT_MTIME as *const u64;
|
||||
mtimecmp.write_volatile(mtime.read_volatile() + interval);
|
||||
|
||||
// prepare information in scratch[] for timervec.
|
||||
// scratch[0..2] : space for timervec to save registers.
|
||||
// scratch[3] : address of CLINT MTIMECMP register.
|
||||
// scratch[4] : desired interval (in cycles) between timer interrupts.
|
||||
let scratch = &mut TIMER_SCRATCH[id];
|
||||
scratch[3] = mtimecmp as u64;
|
||||
scratch[4] = interval;
|
||||
mscratch::write(scratch.as_mut_ptr() as usize);
|
||||
|
||||
// set the machine-mode trap handler
|
||||
mtvec::write(timervec as usize, mtvec::TrapMode::Direct);
|
||||
|
||||
// enable machine-mode interrupts.
|
||||
mstatus::set_mie();
|
||||
|
||||
// enable machime-mode timer interrupts.
|
||||
mie::set_mtimer();
|
||||
}
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
use crate::sync::{Mutex, UPIntrFreeCell};
|
||||
use crate::task::{
|
||||
wakeup_task, block_current_and_run_next, block_current_task, current_task, TaskContext,
|
||||
block_current_and_run_next, block_current_task, current_task, wakeup_task, TaskContext,
|
||||
TaskControlBlock,
|
||||
};
|
||||
use alloc::{collections::VecDeque, sync::Arc};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
use super::UPIntrFreeCell;
|
||||
use crate::task::TaskControlBlock;
|
||||
use crate::task::{wakeup_task, current_task};
|
||||
use crate::task::{block_current_and_run_next, suspend_current_and_run_next};
|
||||
use crate::task::{current_task, wakeup_task};
|
||||
use alloc::{collections::VecDeque, sync::Arc};
|
||||
|
||||
pub trait Mutex: Sync + Send {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
use crate::sync::UPIntrFreeCell;
|
||||
use crate::task::{wakeup_task, block_current_and_run_next, current_task, TaskControlBlock};
|
||||
use crate::task::{block_current_and_run_next, current_task, wakeup_task, TaskControlBlock};
|
||||
use alloc::{collections::VecDeque, sync::Arc};
|
||||
|
||||
pub struct Semaphore {
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
use crate::net::port_table::{listen, PortFd, accept, port_acceptable};
|
||||
use crate::net::port_table::{accept, listen, port_acceptable, PortFd};
|
||||
use crate::net::udp::UDP;
|
||||
use crate::net::{IPv4, net_interrupt_handler};
|
||||
use crate::net::{net_interrupt_handler, IPv4};
|
||||
use crate::task::{current_process, current_task, current_trap_cx};
|
||||
use alloc::sync::Arc;
|
||||
|
||||
|
|
@ -34,11 +34,11 @@ pub fn sys_listen(port: u16) -> isize {
|
|||
// accept a tcp connection
|
||||
pub fn sys_accept(port_index: usize) -> isize {
|
||||
println!("accepting port {}", port_index);
|
||||
|
||||
|
||||
let task = current_task().unwrap();
|
||||
accept(port_index, task);
|
||||
// block_current_and_run_next();
|
||||
|
||||
|
||||
// NOTICE: There does not have interrupt handler, just call it munually.
|
||||
loop {
|
||||
net_interrupt_handler();
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ use switch::__switch;
|
|||
|
||||
pub use context::TaskContext;
|
||||
pub use id::{kstack_alloc, pid_alloc, KernelStack, PidHandle, IDLE_PID};
|
||||
pub use manager::{add_task, wakeup_task, pid2process, remove_from_pid2process};
|
||||
pub use manager::{add_task, pid2process, remove_from_pid2process, wakeup_task};
|
||||
pub use processor::{
|
||||
current_kstack_top, current_process, current_task, current_trap_cx, current_trap_cx_user_va,
|
||||
current_user_token, run_tasks, schedule, take_current_task,
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ use core::arch::{asm, global_asm};
|
|||
use riscv::register::{
|
||||
mtvec::TrapMode,
|
||||
scause::{self, Exception, Interrupt, Trap},
|
||||
sie, sscratch, sstatus, stval, stvec,sip
|
||||
sie, sip, sscratch, sstatus, stval, stvec,
|
||||
};
|
||||
|
||||
global_asm!(include_str!("trap.S"));
|
||||
|
|
@ -95,20 +95,10 @@ pub fn trap_handler() -> ! {
|
|||
Trap::Exception(Exception::IllegalInstruction) => {
|
||||
current_add_signal(SignalFlags::SIGILL);
|
||||
}
|
||||
// Trap::Interrupt(Interrupt::SupervisorTimer) => {
|
||||
// set_next_trigger();
|
||||
// check_timer();
|
||||
// suspend_current_and_run_next();
|
||||
// }
|
||||
Trap::Interrupt(Interrupt::SupervisorSoft) => {
|
||||
//set_next_trigger();
|
||||
const SSIP: usize = 1 << 1;
|
||||
unsafe {
|
||||
asm!("csrc sip, {}", in(reg) SSIP);
|
||||
}
|
||||
//println!("TRAP: ssoft in Kern");
|
||||
Trap::Interrupt(Interrupt::SupervisorTimer) => {
|
||||
set_next_trigger();
|
||||
check_timer();
|
||||
// do not schedule now
|
||||
suspend_current_and_run_next();
|
||||
}
|
||||
Trap::Interrupt(Interrupt::SupervisorExternal) => {
|
||||
crate::board::irq_handler();
|
||||
|
|
@ -161,18 +151,8 @@ pub fn trap_from_kernel(_trap_cx: &TrapContext) {
|
|||
Trap::Interrupt(Interrupt::SupervisorExternal) => {
|
||||
crate::board::irq_handler();
|
||||
}
|
||||
// Trap::Interrupt(Interrupt::SupervisorTimer) => {
|
||||
// //set_next_trigger();
|
||||
// check_timer();
|
||||
// // do not schedule now
|
||||
// }
|
||||
Trap::Interrupt(Interrupt::SupervisorSoft) => {
|
||||
//set_next_trigger();
|
||||
const SSIP: usize = 1 << 1;
|
||||
unsafe {
|
||||
asm!("csrc sip, {}", in(reg) SSIP);
|
||||
}
|
||||
//println!("TRAP: ssoft in Kern");
|
||||
Trap::Interrupt(Interrupt::SupervisorTimer) => {
|
||||
set_next_trigger();
|
||||
check_timer();
|
||||
// do not schedule now
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue